The present invention relates microelectronic devices and more particularly to metal-semiconductor field-effect transistors (MESFETs) formed in silicon carbide.
Electrical circuits requiring high power handling capability ( greater than 20 watts) while operating at high frequencies such as radio frequencies (500 MHz), S-band (3 GHz) and X-band (10 GHz) have in recent years become more prevalent. Because of the increase in high power, high frequency circuits there has been a corresponding increase in demand for transistors which are capable of reliably operating at radio frequencies and above while still being capable of handling higher power loads. Previously, bipolar transistors and power metal-oxide semiconductor field effect transistors (MOSFETs) have been used for high power applications but the power handling capability of such devices may be limited at higher operating frequencies. Junction field-effect transistors (JFETs) were commonly used for high frequency applications but the power handling capability of previously known JFETs also may be limited.
Recently, metal-semiconductor field effect transistors (MESFETs) have been developed for high frequency applications. The MESFET construction may be preferable for high frequency applications because only majority carriers carry current. The MESFET design may be preferred over current MOSFET designs because the reduced gate capacitance permits faster switching times of the gate input. Therefore, although all field-effect transistors utilize only majority carriers to carry current, the Schottky gate structure of the MESFET may make the MESFET more desirable for high frequency applications.
In addition to the type of structurexe2x80x94and perhaps more fundamentallyxe2x80x94the characteristics of the semiconductor material from which a transistor is formed also affects the operating parameters. Of the characteristics which affect a transistor""s operating parameters, the electron mobility, saturated electron drift velocity, electric breakdown field and thermal conductivity may have the greatest effect on a transistor""s high frequency and high power characteristics.
Electron mobility is the measurement of how rapidly an electron is accelerated to its saturated velocity in the presence of an electric field. In the past, semiconductor materials which have a high electron mobility were preferred because more current could be developed with a lesser field, resulting in faster response times when a field is applied. Saturated electron drift velocity is the maximum velocity which an electron can obtain in the semiconductor material. Materials with higher saturated electron drift velocities are preferred for high frequency applications because the higher velocity translates to shorter times from source to drain.
Electric breakdown field is the field strength at which breakdown of the Schottky junction and the current through the gate of the device suddenly increases. A high electric breakdown field material is preferred for high power, high frequency transistors because larger electric fields generally can be supported by a given dimension of material. Larger electric fields allow for faster transients as the electrons can be accelerated more quickly by larger electric fields than by smaller.
Thermal conductivity is the ability of the semiconductor material to dissipate heat. In typical operations, all transistors generate heat. In turn, high power and high frequency transistors usually generate larger amounts of heat than small signal transistors. As the temperature of the semiconductor material increases, the junction leakage currents generally increase and the current through the field effect transistor generally decreases due to a decrease in carrier mobility with an increase in temperature. Therefore, if the heat is dissipated from the semiconductor, the material will remain at a lower temperature and be capable of carrying larger currents with lower leakage currents.
In the past, most high frequency MESFETs have been manufactured of n-type III-V compounds, such as gallium arsenide (GaAs) because of their high electron mobilities. Although these devices provided increased operating frequencies and moderately increased power handling capability, the relatively low breakdown voltage and the lower thermal conductivity of these materials have limited their usefulness in high power applications.
Silicon carbide (SiC) has been known for many years to have excellent physical and electronic properties which should theoretically allow production of electronic devices that can operate at higher temperatures, higher power and higher frequency than devices produced from silicon (Si) or GaAs. The high electric breakdown field of about 4xc3x97106 V/cm, high saturated electron drift velocity of about 2.0xc3x97107 cm/sec and high thermal conductivity of about 4.9 W/cm-xc2x0K indicate that SiC would be suitable for high frequency, high power applications. Unfortunately, difficulty in manufacturing has limited the usefulness of SiC for high power and high frequency applications.
Recently, MESFETs having channel layers of silicon carbide have been produced on silicon substrates (see U.S. Pat. No. 4,762,806 to Suzuki et al and U.S. Pat. No. 4,757,028 to Kondoh et al). Because the semiconductor layers of a MESFET are epitaxial, the layer upon which each epitaxial layer is grown affects the characteristics of the device. Thus, a SiC epitaxial layer grown on a Si substrate generally has different electrical and thermal characteristics then a SiC epitaxial layer grown on a different substrate. Although the SiC on Si substrate devices described in U.S. Pat. Nos. 4,762,806 and 4,757,028 may have exhibited improved thermal characteristics, the use of a Si substrate generally limits the ability of such devices to dissipate heat. Furthermore, the growth of SiC on Si generally results in defects in the epitaxial layers which result in high leakage current when the device is in operation.
Other MESFETs have been developed using SiC substrates. U.S. patent application Ser. No. 07/540,488 filed Jun. 19, 1990 and now abandoned, the disclosure of which is incorporated entirely herein by reference, describes a SiC MESFET having epitaxial layers of SiC grown on a SiC substrate. These devices exhibited improved thermal characteristics over previous devices because of the improved crystal quality of the epitaxial layers grown on SiC substrates. However, to obtain high power and high frequency it may be necessary to overcome the limitations of SiC""s lower electron mobility.
Similarly, commonly assigned U.S. Pat. No. 5,270,554 to co-inventor Palmour describes a SiC MESFET having source and drain contacts formed on n+ regions of SiC and an optional lightly doped epitaxial layer between the substrate and the n-type layer in which the channel is formed. U.S. Pat. No. 5,925,895 to Sriram et al. also describes a SiC MESFET and a structure which is described as overcoming xe2x80x9csurface effectsxe2x80x9d which may reduce the performance of the MESFET for high frequency operation. Sriram et al. also describes SiC MESFETs which use n+ source and drain contact regions as well as a p-type buffer layer. However, despite the performance reported in these patents, further improvements may be made in SiC MESFETs.
Embodiments of the present invention may provide SiC MESFETs formed on a semi-insulating substrate of SiC where the SiC substrate is substantially free of deep level dopants. Forming SiC MESFETs on such semi-insulating substrates may improve performance by reducing back-gating effects which may result from the presence of deep level dopants in the substrate. Buffer layers of p-type, n-type or undoped SiC may be utilized with such semi-insulating SiC substrates in the formation of MESFETs according to embodiments of the present invention.
In additional embodiments of the present invention, a two recess gate structure may be utilized where a cap layer of n-type SiC is formed on an n-type SiC channel layer. A recess is formed in the cap layer and a second recess is formed in the n-type channel layer by forming the second recess in the recess in the cap layer. The Schottky gate contact may then be formed in the second recess.
Further embodiments of the present invention may be provided by SiC MESFETs which utilize a selectively doped p-type buffer layer, where the p-type buffer layer has a carrier concentration of from about 1xc3x971016 to about 1xc3x971017 cmxe2x88x923 and more preferably from about 3 to about 5xc3x971016 cmxe2x88x923. Utilization of such a buffer layer has unexpectedly been found to reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers.
SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process.
Additionally, if a p-type buffer layer is utilized, a contact may be formed to the p-type buffer layer so as to allow grounding of the p-type buffer layer. The contact may be formed on a p+ well region formed in the p-type buffer layer. Optionally, the p-type buffer layer may be formed by two p-type layers where the first layer formed on the substrate has a higher doping level than the second layer which is formed on the first p-type layer.
Particular embodiments of the present invention may provide a high power, high frequency, metal-semiconductor field-effect transistor having a bulk single crystal silicon carbide substrate and an n-type epitaxial layer of n-type conductivity silicon carbide on the substrate. A p-type epitaxial layer of selectively doped p-type conductivity silicon carbide is provided between the substrate and the n-type epitaxial layer. The transistor may also include ohmic contacts for defining a source and a drain as well as a Schottky metal contact.
In other embodiments of the present invention, a high power, high frequency, metal-semiconductor field-effect transistor may be provided having an n-type layer of n-type conductivity silicon carbide on a silicon carbide substrate and a p-type layer of p-type conductivity silicon carbide between the substrate and the n-type layer. Ohmic contacts are provided on portions of the n-type layer and spaced apart which respectively define a source and a drain. A region of chromium is also provided on a portion of the n-type layer that is between the ohmic contacts and thereby between the source and the drain so as to provide a Schottky metal contact for forming an active channel in the n-type layer between the source and the drain when a bias is applied to the Schottky metal contact.
In further embodiments of the present invention, an overlayer is formed on the ohmic contacts and the Schottky metal contact. Preferably, the ohmic contacts are formed of nickel and the overlayer includes layers of titanium, platinum and gold.
Furthermore, the layers of the transistors according to the present invention may form a mesa having sidewalls extending downward from the n-type layer into the p-type layer which define the periphery of the transistors. Optionally, the sidewalls of the mesa may extend downward into the substrate. A passivation layer may also be provided on the sidewalls of the mesa and exposed portions of the n-type epitaxial layer. Preferably, the passivation layer is an ONO passivation layer.
In still further embodiments of the present invention, the Schottky metal contact is recessed in the active channel portion of the n-type epitaxial layer. The Schottky metal contact may also be a mushroom gate contact. The Schottky metal contact may also include an overlayer having layers of platinum and gold.
Metallization may also be formed on the substrate opposite the n-type layer. Preferably, the metallization includes layers of titanium, platinum and gold coated with an overlayer of eutectic alloy of AuGe.
The substrate may also be semi-insulating silicon carbide. While in particular embodiments it is preferred to utilize a semi-insulating substrate which is substantially free of deep level dopants, in other embodiments a semi-insulating silicon carbide substrate may be silicon carbide with a deep level dopant incorporated therein. The deep level dopant may be vanadium. Preferably, the semi-insulating substrate has a resistance of greater than about 10,000 xcexa9-cm.
In still further embodiments of the present invention, the ohmic contacts may be formed on regions of n+ silicon carbide which may be formed in the n-type epitaxial layer by ion implantation or, alternatively, formed directly on the n-type epitaxial layer.
Aspects of the present invention also may provide methods of fabricating a metal-semiconductor field-effect transistor by forming a p-type epitaxial layer of selectively doped p-type conductivity silicon carbide on a single crystal silicon carbide substrate, wherein the p-type conductivity silicon carbide has a carrier concentration of from about 1xc3x971016 to about 1xc3x971017 cmxe2x88x923, the forming an n-type epitaxial layer of n-type conductivity silicon carbide on the p-type epitaxial layer, then forming ohmic contacts on the n-type epitaxial layer that respectively define a source and a drain and forming a Schottky metal contact on the n-type epitaxial layer that is between the ohmic contacts and thereby between the source and the drain. The n-type epitaxial layer and the p-type epitaxial layer may be etched to form a mesa. Furthermore in a preferred embodiment, the formation of ohmic contacts and a Schottky gate contact are preceded by etching the n-type epitaxial layer and the p-type epitaxial layer to form a mesa and forming an ONO passivation layer on the exposed surfaces of the mesa.
In particular embodiments of the present invention, the ONO passivation layer is formed by high temperature annealing exposed portions of the substrate, p-type epitaxial layer and n-type epitaxial layer in an H2 ambient and then forming an SiO2 layer on the exposed portions of the substrate, p-type epitaxial layer and n-type epitaxial layer. The SiO2 layer is then argon annealed and oxidized. A layer of Si3N4 is then deposited on the oxidized SiO2 layer and oxidized to provide the ONO structure.
In particular embodiments of the present invention, the high temperature anneal is carried out at a temperature of greater than about 900xc2x0 C. for a time of from about 15 minutes to about 2 hours. Furthermore, the argon anneal may be carried out at a temperature of about 1200xc2x0 C. for a time of about 1 hour.
The SiO2 layer may also be formed to a thickness of from about 50 to about 500 xc3x85. Preferably, the SiO2 layer is formed through a dry oxide process at a temperature of about 1200xc2x0 C. Also, the SiO2 layer is preferably oxidized in a wet environment at a temperature of about 950xc2x0 C. for a time of about 180 minutes.
The layer of Si3N4 may be deposited to a thickness of from about 200 to about 2000 xc3x85. Preferably, the layer of Si3N4 is deposited through chemical vapor deposition such as PECVD or LPCVD. The Si3N4 layer is also preferably oxidized in a wet environment at a temperature of about 950xc2x0 C. for a time of about 180 minutes. The Si3N4 layer may be oxidized to provide an oxide layer having a thickness of from about 20 to about 200 xc3x85.
In other embodiments of the present invention, a gate recess is formed in the n-type epitaxial layer and the Schottky gate contact formed in the gate recess. Preferably, the gate recess is formed by etching through the ONO passivation layer and into the n-type epitaxial layer so as to provide a gate recess in the n-type epitaxial layer and the Schottky gate contact formed in the gate recess utilizing the ONO passivation layer as a mask. Furthermore, the step of etching through the ONO passivation layer may be followed by patterning the ONO passivation layer so as to provide a ledge in sidewalls of the opening of the ONO passivation layer for the gate recess. A mushroom gate structure may then be formed in the gate recess and on the sidewalls and ledge of the ONO passivation layer. The etching of the ONO passivation layer may be carried out by Electron Cyclotron Resonance or Inductively Coupled Plasma etching.
In a still further embodiment of the present invention, n+ well regions are implanted in the n-type epitaxial layer so as to provide source and drain regions and the ohmic contacts formed on the n+ well regions.
In a still further aspect of the present invention, the substrate is thinned and a metallization layer formed on the substrate opposite the p-type epitaxial layer. The metallization layer may be formed by forming a titanium layer on the substrate opposite the p-type epitaxial layer, then forming a layer of platinum on the titanium layer; and then forming a layer of gold on the layer of platinum. A layer of a eutectic alloy of AuGe may also be formed on the layer of gold.
In another aspect of the present invention methods of fabricating a gate structure for a silicon carbide field effect transistor is provided by forming an ONO passivation layer on exposed surfaces of a mesa terminated silicon carbide field effect transistor, forming a gate window in the ONO passivation layer, forming a gate recess in a channel layer of the mesa terminated silicon carbide transistor and forming a gate contact in the gate recess in the channel layer. The ONO passivation layer is preferably formed as described above. Furthermore, the mushroom gate structure may also be formed as described above.
In still further embodiments of the present invention, methods of fabricating a passivation layer of a silicon carbide semiconductor device are provided by forming an oxide layer on the silicon carbide semiconductor device and then annealing the oxide layer in a NO environment. The oxide layer may be thermally grown or deposited. Furthermore, the anneal in the NO environment may be followed by depositing a layer of Si3N4 on the oxidized SiO2 layer and then oxidizing the layer of Si3N4.
In particular embodiments, the oxide layer may be formed by high temperature annealing exposed portions of the substrate, p-type epitaxial layer and n-type epitaxial layer in an H2 ambient and then forming an SiO2 layer on the exposed portions of the substrate, p-type epitaxial layer and n-type epitaxial layer, argon annealing the SiO2 layer and oxidizing the SiO2 layer.
In still further embodiments of the present invention, a double recessed gate MESFET may be fabricated by forming an n-type epitaxial layer of n-type conductivity silicon carbide on a silicon carbide substrate, forming ohmic contacts on the n-type epitaxial layer that respectively define a source and a drain, forming a cap layer of n-type silicon carbide on the n-type epitaxial layer, forming a first recess in the cap layer, forming a second recess in the n-type epitaxial layer, wherein the recess in the n-type epitaxial layer is within the first recess in the cap layer, and forming a Schottky metal contact on the n-type epitaxial layer that is between the ohmic contacts and thereby between the source and the drain to form an active channel in the n-type epitaxial layer between the source and the drain when a bias is applied to the Schottky metal contact wherein the Schottky metal contact is within the recess in the n-type epitaxial layer.
In particular embodiments, the formation of an n-type epitaxial layer and a cap layer are provided by epitaxially growing the n-type epitaxial layer and the cap layer in a single growth step. Furthermore, in still further embodiments, an n-type dopant concentration in the single growth step may be changed to grow the cap layer.
In yet additional embodiments of the present invention, the first recess in the cap layer may be formed by patterning the cap layer to form the first recess. Furthermore, a mesa having sidewalls which extend through the cap layer and the n-type epitaxial layer may also be formed. In such embodiments, the patterning of the cap layer to form the first recess may be followed by forming an ONO passivation layer on exposed surfaces of the mesa and the first recess, forming a gate window in the ONO passivation layer, wherein the gate window is within the first recess, forming the second recess in n-type epitaxial layer and forming a gate contact in the second recess.
In still further embodiments, the substrate may be formed by forming a semi-insulating SiC substrate which is substantially free of deep-level dopants. Also, a buffer layer may be formed between the substrate and the n-type epitaxial layer. The buffer layer may be undoped SiC, n-type SiC or p-type SiC. If the buffer layer is p-type SiC, in particular embodiments, the p-type epitaxial layer may be formed by forming a first p-type epitaxial layer on the substrate and forming a second p-type epitaxial layer on the first p-type epitaxial layer, wherein the second p-type epitaxial layer has a lower dopant concentration than the first p-type epitaxial layer.
In still further embodiments, an ohmic contact is formed to the p-type epitaxial layer. Furthermore, p-type dopants may be implanted in the p-type epitaxial layer so as to provide a region of p-type conductivity silicon carbide having a higher carrier concentration than the p-type epitaxial layer the ohmic contact formed on the implanted region. The ohmic contact may be formed by etching a ground contact window through the cap layer and the n-type epitaxial layer in a region adjacent a source region of the MESFET and forming the ohmic contact in the ground contact window.
The advantages and features of the invention, and the manner in which the same are accomplished, will become more readily apparent upon consideration of the following detailed description of the invention taken in conjunction with the accompanying drawings, which illustrate preferred and exemplary embodiments, and wherein: